1. Field of the Invention
This invention relates to a dynamic storage device utilizing the concept of trapping minority carriers for data storage.
2. Prior Art
This invention is related to a copending application entitled "High Density Memory Cell" filed on the same date as this application by Narasipur G. Anantha et al and commonly assigned with this application. This copending application discloses a dynamic storage device having a high-low junction of N-type silicon with a P-type injector region separating source and drain regions. This invention is an improvement of the invention defined in that copending application.
The prior art identified in the copending application, namely U.S. Pat. Nos. 3,852,800, 4,122,543, and 4,164,751 shows various charge storage concepts. In particular, the prior art utilizes MIS capacitors, PN junction capacitance, and depletion layer capacitance. The prior art does not show high-low-high junction trapping of minority carriers used for data storage.
While the copending application represents a significant improvement over that prior art, it requires an external diode as the gating device for each cell when forming the two dimensional storage array. The requirement of the additional diode decreases the ability to achieve extremely high packing densities, a standing requirement in this technology. Accordingly, the elimination of external elements used to form a storage array represents potentially a significant improvement in achieving high packing densities.
Moreover, prior art dynamic memories require thin film dielectrics that are difficult to manufacture. In the case of charge storage on P+/N+ junction capacitance, leakage due to tunneling requires the data to be refreshed more frequently. A large number of masks are generally required in the formation of those devices and while the processing steps per se are well established in the art, cost and yield considerations remain as areas requiring improved process steps.